The flashcart uses (rev4) or emulates (rev5+) a 2003 mapper. Most of its functionality (banking, flash access via SRAM) is provided.

• JS28F00AM29EWHA (1Gbit NOR flash, accessible as 16 64Mbit slots)
• 4Mbit SRAM

AVR wake/sleep is controlled using 2003 GPIO bit 3.

To wake up the AVR:

• port 0xCD = 0x08
• port 0xCC = 0x08
• port 0xCD = 0x00

One should wait around 12 ms (maybe less?) after sending this signal to ensure the AVR is awake.

To put the AVR to sleep:

• port 0xCD = 0x08
• port 0xCC = 0x00

The flashcart uses invalid RTC date/time values to provide custom commands. For this to work, the AVR must be awake (see above).

Format: RTC command 0x14 with parameters [0xA1, slot, 0, 0, 0, 0, 0, 0].

Description: Configure the visible slot, from 0 to 15.

• RTC port 0xCA always returns either 0x94 (while a command is being processed) or 0x84 (when it is done). It is unknown if anything beyond the “set slot ID” command is emulated.
• All other bytes in the 0xC0~0xDF space have all 8 bits writable. Bytes 0xE0~0xFF are not writable and always return 0x00.
• Port 0xCF is not a mirror of byte 0xC0 and has no effect, though it is set to 0x3F on boot just like byte 0xC0.
• Setting bit 0 of port 0xCE disconnects the NOR flash from the ROM bus (memory area 0x20000 - 0xFFFFF returns 0xFF bytes).

Power on state: 3F FF FF FF 00 00 00 00 00 00 84 00 00 00 00 3F FF 03 FF 03 FF 03 00 00 00 00 00 00 00 00 00 00